The trend in semiconductor integrated circuitry continues to involve a decrease in the size of individual semiconductor structures accompanied by an increase in the complexity and number of such structures aggregated on a single semiconductor integrated chip. Single semiconductor devices have been grouped into integrated circuits, which in turn have been further densified into large scale integrated semiconductor systems. Structure flaws which previously passed unnoticed in individual semiconductor devices and integrated semiconductor circuit systems have become significant, debilitating structural shortcomings in intensely miniaturized, densely packed large scale integration efforts.
In memory cells and in logic cells, for example, it has been common to interconnect the gate of a transistor device through the surface of the semiconductor substrate upon which it is located to various diffusion areas formed in the surface of that substrate at locations remote from the transistor device itself. The problems inherent in accomplishing this objective are numerous. Further, such problems become more prominent as the semiconductor devices involved are rendered in progressively smaller scale and in increasingly densified arrangements with other devices.
An example of a portion of such a typical SRAM memory cell is shown schematically in FIG. 1 by reference numeral 10. Such comprises a pair of transistors T.sub.1 and T.sub.2. These transistors are each series connected with a respective biasing resistor R.sub.1 and R.sub.2 between a biased voltage V+ and ground. Transistor T.sub.1 comprises a source S.sub.1, a drain D.sub.1, and a gate G.sub.1 therebetween for governing current flow through transistor T.sub.1. Correspondingly, transistor T.sub.2 comprises a source S.sub.2, a drain D.sub.2, and a gate G.sub.2 located therebetween.
It is common in configuring a pair of transistors into a memory cell, such as transistors T.sub.1 and T.sub.2, to cross-couple the gate of one transistor to the source or drain of the other. Thus, G.sub.1 of transistor T.sub.1 is coupled through a current path 12 to the diffusion region which functions as the drain D.sub.2 of transistor T.sub.2. Similarly, gate G.sub.2 of transistor T.sub.2 is coupled by another current pathway 14 to the diffusion region which functions as the drain D.sub.1 of transistor T.sub.1.
Examples of prior art methods and problems associated therewith for providing such interconnections are described in the Background and Invention Description sections of my issued U.S. Pat. No. 5,064,776, which is hereby incorporated by reference. Such techniques employ single layer conductive gates and interconnects.
Another prior art method involving multiple layer conductive gates and interconnects is described below with reference to FIGS. 2-5. FIG. 2 illustrates a semiconductor silicon wafer 16 having a p-type conductivity well 18 and an upper substrate surface 20. A gate insulative layer 22 and field oxide regions 24 have been provided, as shown. A first polysilicon layer 26 is deposited, and an etch conducted to produce buried contact 28. A conductivity enhancing impurity doping is conducted to produce an active n+ region 30.
Referring to FIG. 3, a second polysilicon layer 32 is deposited.
Referring to FIG. 4, polysilicon layers 32 and 26, and oxide layer 22 are etched as shown to define gate G.sub.1, gate G.sub.2 and interconnect 14. A doped diffusion is conducted to generate n+ active areas 33 and 35 for transistor G.sub.1. Active areas 30 and 35 are intended to comprise a composite drain D.sub.1 of FIG. 1, but are undesirably separated as shown. Such results from a requirement that the photoresist patterning be conducted such that interconnect polysilicon layer 32 extends beyond the left edge of active area region 30, as shown in FIG. 4, to assure its overlapping with oxide material 22 in the event of misalignment. Were such overlap not provided and misalignment occurs, an undesirable trench would be etched into active area 30 during the poly 32 and poly 26 etch. With the overlap as shown, the poly 32 and poly 26 etch will stop on gate oxide 22, thereby assuring no trenching.
Referring to FIG. 5, oxide spacers 34 are provided about gates G.sub.1 and gates G.sub.2. Heating of the wafer during various processing steps causes n+ implant regions 30 and 35 to desirably migrate inward somewhat. However, the migration may not be sufficient to create a common active area 30 and 35 (D.sub.1 as shown in FIG. 1) as is necessary for desired circuit operation.
It would be desirable to overcome these and other problems associated with the prior art in providing electrical contact between a gate of a transistor device and an active area remote of the transistor device.